AS7C1025B
®
Write waveform 2 (CE controlled)
10,11
t
AW
Address
t
AS
CE
t
WP
WE
t
WZ
D
IN
D
OUT
t
DW
Data valid
t
DH
t
CW
t
WC
t
AH
t
WR
AC test conditions
–
–
–
–
Output load: see Figure B.
Input pulse level: GND to 3.5 V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5 V.
+5 V
480
Ω
Thevenin equivalent:
168
Ω
+3.5 V
GND
90%
10%
2 ns
90%
10%
D
OUT
255
Ω
C
13
D
OUT
+1.728 V
Figure A: Input pulse
GND
Figure B: 5 V Output load
Notes
1
2
3
4
5
6
7
8
9
10
11
12
13
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
This parameter is sampled, but not 100% tested.
For test conditions, see
AC Test Conditions,
Figures A and B.
t
CLZ
and t
CHZ
are specified with CL = 5 pF, as in Figure B. Transition is measured
±500
mV from steady-state voltage.
This parameter is guaranteed, but not 100% tested.
WE is high for read cycle.
CE and OE are low for read cycle.
Address is valid prior to or coincident with CE transition low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
N/A
All write cycle timings are referenced from the last valid address to the first transitioning address.
N/A.
C = 30 pF, except all high Z and low Z parameters where C = 5 pF.
3/26/04, v. 1.3
Alliance Semiconductor
P. 6 of 9
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
