AS7C32098A
®
Write waveform 3
9
t
WC
t
AH
t
WR
Address
t
AS
t
CW
CE
t
AW
t
BW
LB, UB
WE
Data
IN
Data
OUT
High Z
t
WZ
Data undefined
t
WP
t
DW
Data valid
t
DH
High Z
AC test conditions
-
-
-
-
Output load: see Figure B.
Input pulse level: GND to 3.0V. See Figure A.
Input rise and fall times: 2 ns. See Figure A.
Input and output timing reference levels: 1.5V.
+3.0V
GND
90%
10%
2 ns
Figure A: Input pulse
90%
10%
D
OUT
350Ω
+3.3V
320Ω
C
10
Thevenin equivalent:
168Ω
D
OUT
+1.728V
GND
Figure B: 3.3V Output load
Notes
1
2
3
4
5
6
7
8
9
10
During V
CC
power-up, a pull-up resistor to V
CC
on CE is required to meet I
SB
specification.
For test conditions, see
AC Test Conditions,
Figures A and B.
t
CLZ
and t
CHZ
are specified with C
L
= 5pF as in Figure B. Transition is measured ±500mV from steady-state voltage.
This parameter is guaranteed, but not tested.
WE is High for read cycle.
CE and OE are Low for read cycle.
Address valid prior to or coincident with CE transition Low.
All read cycle timings are referenced from the last valid address to the first transitioning address.
All write cycle timings are referenced from the last valid address to the first transitioning address.
C=30pF, except on High Z and Low Z parameters, where C=5pF.
2/24/05,v. 1.0
Alliance Semiconductor
P. 7 of 10
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
