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AS7C33512PFS36A-166TQIN 参数 Datasheet PDF下载

AS7C33512PFS36A-166TQIN图片预览
型号: AS7C33512PFS36A-166TQIN
PDF下载: 下载PDF文件 查看货源
内容描述: 3.3V 512K X 32/36流水线突发同步SRAM [3.3V 512K x 32/36 pipelined burst synchronous SRAM]
分类和应用: 静态存储器
文件页数/大小: 19 页 / 542 K
品牌: ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
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AS7C33512PFS32A  
AS7C33512PFS36A  
®
Write enable truth table (per byte)  
Function  
GWE BWE  
BWa  
X
BWb  
X
BWc  
BWd  
X
L
H
H
H
H
H
X
L
L
L
H
L
X
L
Write All Bytes  
L
L
L
Write Byte a  
L
H
H
L
H
Write Byte c and d  
H
H
L
X
X
X
H
X
Read  
H
H
H
Key: X = don’t care, L = low, H = high, n = a, b, c, d; BWE, BWn = internal write signal.  
Asynchronous Truth Table  
Operation  
Snooze mode  
ZZ  
H
L
OE  
X
I/O Status  
High-Z  
L
Dout  
Read  
L
H
High-Z  
Write  
L
X
Din, High-Z  
High-Z  
Deselected  
L
X
Notes:  
1. X means “Don’t Care”  
2. ZZ pin is pulled down internally  
3. For write cycles that follows read cycles, the output buffers must be disabled with OE, otherwise data bus contention will occur.  
4. Snooze mode means power down state of which stand-by current does not depend on cycle times  
5. Deselected means power down state of which stand-by current depends on cycle times  
Burst sequence table  
Interleaved burst address (LBO = 1)  
Linear burst address (LBO = 0)  
A1 A0  
0 0  
A1 A0  
0 1  
A1 A0  
1 0  
A1 A0  
1 1  
A1 A0  
0 0  
A1 A0  
0 1  
A1 A0  
1 0  
A1 A0  
1 1  
Starting Address  
First Increment  
Second Increment  
Third Increment  
Starting Address  
First Increment  
Second Increment  
Third Increment  
0 1  
0 0  
1 1  
1 0  
0 1  
1 0  
1 1  
0 0  
1 0  
1 1  
0 0  
0 1  
1 0  
1 1  
0 0  
0 1  
1 1  
1 0  
0 1  
0 0  
1 1  
1 0  
0 1  
1 0  
12/23/04, v 2.6  
Alliance Semiconductor  
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