October 2003
rev 1.0
ASM706 P/ R/ S/ T/ J
ASM708 R/ S/ T/ J
Pin Description
Pin Number
ASM706P
DIP/
SO
MicroSO
ASM706R/S/T/J
DIP/
SO
MicroSO
ASM708R/S/T/J
DIP/
SO
MicroSO
Manual reset input. The active LOW input triggers
a reset pulse. It is pulled HIGH by a 20kΩ pull-up
resistor. It is compatible with TTL/CMOS signals
when V
CC
= 5V. It can be shorted to ground
through a mechanical switch. Leave folating or
connect to V
CC
if the function is not used.
2
3
4
4
5
6
2
3
4
4
5
6
2
3
4
4
5
6
V
CC
GND
PFI
Monitored power supply input.
Ground.
Power-fail input voltage monitor. With PFI less
than 1.25V, PFO goes LOW. Connect PFI to
Ground when not in use.
Power-fail output. The output is active LOW and
sinks current when PFI is less than 1.25V. If not
used, leave the pin unconnected.
Watchdog input. WDI controls the internal watch-
dog timer. A HIGH or LOW signal for 1.6sec at
WDI allows the internal timer to run-out, setting
WDO low. A rising or falling edge must occur at
WDI within 1.6 seconds or WDO goes LOW. The
watchdog function is disabled by floating WDI. The
internal watchdog timer clears when: RESET is
asserted; WDI is three-stated ; or WDI sees a ris-
ing or falling edge.
Not Connected
Active LOW reset output. Pulses LOW for 200ms
when triggered, and stays LOW whenever V
CC
is
-
-
7
1
7
1
RESET
below the reset threshold. RESET remains LOW
for 200ms after V
CC
rises above the reset thresh-
old or MR goes from HIGH to LOW. A watchdog
timeout will not trigger RESET unless WDO is con-
nected to MR.
Name
Function
1
3
1
3
1
3
MR
5
7
5
7
5
7
PFO
6
8
6
8
-
-
WDI
-
-
-
-
6
8
NC
3/3.3/4.0 V µP Supervisor Circuits
Notice: The information in this document is subject to change without notice
3 of 16
ALSC [ ALLIANCE SEMICONDUCTOR CORPORATION ]
