Chapter 1: Arria GX Device Family Overview
Features
1–3
Table 1–1.
Arria GX Device Features (Part 2 of 2)
EP1AGX20C
Feature
C
Source-
synchronous
transmit
channels
M512 RAM
blocks
(32 × 18 bits)
M4K RAM
blocks
(128 × 36
bits)
M-RAM
blocks
(4096 × 144
bits)
Total RAM
bits
Embedded
multipliers
(18 × 18)
DSP blocks
PLLs
Maximum
user I/O pins
C
D
C
D
C
D
E
E
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
29
29
29
29
29, 42
29
29
42
45
166
197
313
326
478
118
140
242
252
400
1
1
2
2
4
1,229,184
1,348,416
2,475,072
2,528,640
4,477,824
40
10
4
230, 341
230
56
14
4
341
4
229
104
26
4, 8
350, 514
229
4
128
32
8
350
514
176
44
8
538
Arria GX devices are available in space-saving FBGA packages (refer to
All
Arria GX devices support vertical migration within the same package. With vertical
migration support, designers can migrate to devices whose dedicated pins,
configuration pins, and power pins are the same for a given package across device
densities. For I/O pin migration across densities, the designer must cross-reference
the available I/O pins with the device pin-outs for all planned densities of a given
package type to identify which I/O pins are migratable.
Table 1–2.
Arria GX Package Options (Pin Counts and Transceiver Channels) (Part 1 of 2)
Source-Synchronous Channels
Device
Transceiver
Channels
4
4
4
4
8
8
Receive
31
31
31
31
31
31, 42
Transmit
29
29
29
29
29
29, 42
Maximum User I/O Pin Count
484-Pin FBGA
(23 mm)
230
230
229
229
—
—
780-Pin FBGA
(29 mm)
341
—
—
—
341
350
1152-Pin
FBGA
(35 mm)
—
—
—
—
—
514
EP1AGX20C
EP1AGX35C
EP1AGX50C
EP1AGX60C
EP1AGX35D
EP1AGX50D
© December 2009
Altera Corporation
Arria GX Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
