1–2
Chapter 1: Arria GX Device Family Overview
Features
■
Main device features:
■
TriMatrix memory consisting of three RAM block sizes to implement true
dual-port memory and first-in first-out (FIFO) buffers with performance up to
380 MHz
Up to 16 global clock networks with up to 32 regional clock networks per
device
High-speed DSP blocks provide dedicated implementation of multipliers,
multiply-accumulate functions, and finite impulse response (FIR) filters
Up to four enhanced phase-locked loops (PLLs) per device provide spread
spectrum, programmable bandwidth, clock switch-over, and advanced
multiplication and phase shifting
Support for numerous single-ended and differential I/O standards
High-speed source-synchronous differential I/O support on up to 47 channels
Support for source-synchronous bus standards, including SPI-4 Phase 2
(POS-PHY Level 4), SFI-4.1, XSBI, UTOPIA IV, NPSI, and CSIX-L1
Support for high-speed external memory including DDR and DDR2 SDRAM,
and SDR SDRAM
Support for multiple intellectual property megafunctions from Altera
®
MegaCore
®
functions and Altera Megafunction Partners Program (AMPP
SM
)
Support for remote configuration updates
■
■
■
■
■
■
■
■
■
lists Arria GX device features for FineLine BGA (FBGA) with flip chip
packages.
Table 1–1.
Arria GX Device Features (Part 1 of 2)
EP1AGX20C
Feature
C
Package
484-pin,
780-pin
(Flip chip)
8,632
21,580
C
484-pin
(Flip chip)
D
780-pin
(Flip chip)
C
484-pin
(Flip chip)
D
780-pin,
1152-pin
(Flip chip)
13,408
33,520
20,064
50,160
24,040
60,100
36,088
90,220
C
484-pin
D
780-pin
E
E
1152-pin
(Flip chip)
1152-pin
(Flip chip) (Flip chip) (Flip chip)
EP1AGX35C/D
EP1AGX50C/D
EP1AGX60C/D/E
EP1AGX90E
ALMs
Equivalent
logic
elements
(LEs)
Transceiver
channels
Transceiver
data rate
Source-
synchronous
receive
channels
4
600 Mbps
to 3.125
Gbps
31
4
8
4
8
4
8
12
12
600 Mbps
to 3.125
Gbps
47
600 Mbps to 3.125
Gbps
600 Mbps to 3.125
Gbps
600 Mbps to 3.125 Gbps
31
31
31
31, 42
31
31
42
Arria GX Device Handbook, Volume 1
© December 2009
Altera Corporation