Cyclone FPGA Family Data Sheet
Preliminary Information
Logic Array
Blocks
Each LAB consists of 10 LEs, LE carry chains, LAB control signals, a local
interconnect, look-up table (LUT) chain, and register chain connection
lines. The local interconnect transfers signals between LEs in the same
LAB. LUT chain connections transfer the output of one LE’s LUT to the
adjacent LE for fast sequential LUT connections within the same LAB.
Register chain connections transfer the output of one LE’s register to the
adjacent LE’s register within an LAB. The Quartus
®
II Compiler places
associated logic within an LAB or adjacent LABs, allowing the use of local,
LUT chain, and register chain connections for performance and area
efficiency.
Figure 2
details the Cyclone LAB.
Figure 2. Cyclone LAB Structure
Row Interconnect
Column Interconnect
Direct link
interconnect from
adjacent block
Direct link
interconnect from
adjacent block
Direct link
interconnect to
adjacent block
Direct link
interconnect to
adjacent block
LAB
Local Interconnect
6
Altera Corporation
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