Preliminary Information
Cyclone FPGA Family Data Sheet
Logic Elements
The smallest unit of logic in the Cyclone architecture, the LE, is compact
and provides advanced features with efficient logic utilization. Each LE
contains a four-input LUT, which is a function generator that can
implement any function of four variables. In addition, each LE contains a
programmable register and carry chain with carry select capability. A
single LE also supports dynamic single bit addition or subtraction mode
selectable by an LAB-wide control signal. Each LE drives all types of
interconnects: local, row, column, LUT chain, register chain, and direct
link interconnects. See
Figure 5.
Figure 5. Cyclone LE
Register chain
routing from
previous LE
LAB-wide
Register Bypass
Synchronous
Load
LAB-wide
Packed
Synchronous
Register Select
Clear
LAB Carry-In
addnsub
Carry-In1
Carry-In0
Programmable
Register
LUT chain
routing to next LE
Row, column,
and direct link
routing
data1
data2
data3
data4
ENA
CLRN
Look-Up
Table
(LUT)
Carry
Chain
Synchronous
Load and
Clear Logic
PRN/ALD
D
Q
ADATA
Row, column,
and direct link
routing
labclr1
labclr2
labpre/aload
Chip-Wide
Reset
Asynchronous
Clear/Preset/
Load Logic
Local Routing
Clock &
Clock Enable
Select
labclk1
labclk2
labclkena1
labclkena2
Register
Feedback
Register chain
output
Carry-Out0
Carry-Out1
LAB Carry-Out
Altera Corporation
9
ALTERA [ ALTERA CORPORATION ]
