Tables 4–125 and 4–126 show the high-speed I/O timing for Stratix devices.
Table 4–125. High-Speed I/O Specifications for Flip-Chip Packages (Part 1 of 4) Notes (1), (2)
-5 Speed Grade
Min Typ Max
-6 Speed Grade
Min Typ Max
-7 Speed Grade
Min Typ Max
-8 Speed Grade
Min Typ Max
Symbol
Conditions
Unit
MHz
MHz
MHz
MHz
MHz
fHSCLK (Clock
frequency)
(LVDS,
LVPECL,
HyperTransport
technology)
W = 4 to 30
(Serdes used)
10
210
231
420
462
717
10
210
231
420
462
717
10
156
231
312
462
624
10
115.5
W = 2 (Serdes
bypass)
50
50
50
50
231
W = 2 (Serdes
used)
150
100
300
150
100
300
150
100
300
150
100
300
231
f
W
HSCLK = fHSDR /
W = 1 (Serdes
bypass)
462
W = 1 (Serdes
used)
462
f
HSDR Device
J = 10
J = 8
J = 7
J = 4
J = 2
300
300
300
300
100
100
840
840
840
840
462
462
300
300
300
300
100
100
840
840
840
840
462
462
300
300
300
300
100
100
640
640
640
640
640
640
300
300
300
300
100
100
462
462
462
462
462
462
Mbps
Mbps
Mbps
Mbps
Mbps
Mbps
operation
(LVDS,
LVPECL,
HyperTransport
technology)
J = 1 (LVDS
and LVPECL
only)
ALTERA [ ALTERA CORPORATION ]
