DC & Switching Characteristics
High-Speed I/O
Specification
provides high-speed timing specifications definitions.
Table 4–124. High-Speed Timing Specifications & Terminology
High-Speed Timing Specification
t
C
f
HSCLK
t
RISE
t
FALL
Timing unit interval (TUI)
Terminology
High-speed receiver/transmitter input and output clock period.
High-speed receiver/transmitter input and output clock frequency.
Low-to-high transmission time.
High-to-low transmission time.
The timing budget allowed for skew, propagation delays, and data
sampling window. (TUI = 1/(Receiver Input Clock Frequency
×
Multiplication Factor) = t
C
/w).
Maximum LVDS data transfer rate (f
HSDR
= 1/TUI).
The timing difference between the fastest and slowest output edges,
including t
CO
variation and clock skew. The clock is included in the TCCS
measurement.
The period of time during which the data must be valid to be captured
correctly. The setup and hold times determine the ideal strobe position
within the sampling window.
SW = t
SW
(max) – t
SW
(min).
Peak-to-peak input jitter on high-speed PLLs.
Peak-to-peak output jitter on high-speed PLLs.
Duty cycle on high-speed transmitter output clock.
Lock time for high-speed transmitter and receiver PLLs.
Deserialization factor (width of internal data bus).
PLL multiplication factor.
f
HSDR
Channel-to-channel skew (TCCS)
Sampling window (SW)
Input jitter (peak-to-peak)
Output jitter (peak-to-peak)
t
DUTY
t
LOCK
J
W
Altera Corporation
July 2005
4–87
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
