Stratix Architecture
Table 2–12 shows the input and output data signal connections for the
column units (B1 to B6 and A1 to A6). It also shows the address and
control signal input connections to the row units (R1 to R11).
Table 2–12. M-RAM Row & Column Interface Unit Signals
Unit Interface Block
Input SIgnals
Output Signals
R1
R2
R3
addressa[7..0]
addressa[15..8]
byte_enable_a[7..0]
renwe_a
R4
R5
R6
-
-
clock_a
clocken_a
clock_b
clocken_b
R7
R8
R9
-
-
byte_enable_b[7..0]
renwe_b
R10
R11
B1
B2
B3
B4
B5
B6
A1
A2
A3
A4
A5
A6
addressb[15..8]
addressb[7..0]
datain_b[71..60]
datain_b[59..48]
datain_b[47..36]
datain_b[35..24]
datain_b[23..12]
datain_b[11..0]
datain_a[71..60]
datain_a[59..48]
datain_a[47..36]
datain_a[35..24]
datain_a[23..12]
datain_a[11..0]
dataout_b[71..60]
dataout_b[59..48]
dataout_b[47..36]
dataout_b[35..24]
dataout_b[23..12]
dataout_b[11..0]
dataout_a[71..60]
dataout_a[59..48]
dataout_a[47..36]
dataout_a[35..24]
dataout_a[23..12]
dataout_a[11..0]
Altera Corporation
July 2005
2–43
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
