TriMatrix Memory
Figure 2–27. Read/Write Clock Mode in Simple Dual-Port Mode Notes (1), (2)
8 LAB Row
Clocks
Memory Block
256 × 16
8
512 × 8
1,024 × 4
2,048 × 2
4,096 × 1
data[ ]
D
ENA
Q
Data In
To MultiTrack
Interconnect
Data Out
D
Q
ENA
address[ ]
Read Address
Write Address
Byte Enable
D
Q
Q
Q
ENA
wraddress[ ]
D
ENA
byteena[ ]
rden
D
ENA
Read Enable
D
Q
ENA
wren
outclken
Write
Pulse
Generator
D
ENA
Q
inclken
wrclock
Write Enable
rdclock
Notes to Figure 2–27:
(1) All registers shown except the rdenregister have asynchronous clear ports.
(2) Violating the setup or hold time on the address registers could corrupt the memory contents. This applies to both
read and write operations.
2–50
Altera Corporation
July 2005
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
