Stratix Architecture
Figure 2–8. Carry Select Chain
LAB Carry-In
A1
B1
A2
B2
0
LE1
1
Sum1
LAB Carry-In
Carry-In0
Carry-In1
LE2
Sum2
LUT
data1
data2
Sum
LUT
A3
B3
A4
B4
LE3
Sum3
LE4
Sum4
LUT
A5
B5
LE5
Sum5
LUT
0
A6
B6
A7
B7
A8
B8
A9
B9
A10
B10
LE6
1
Sum6
Carry-Out0
Carry-Out1
LE7
Sum7
LE8
Sum8
LE9
Sum9
LE10
Sum10
LAB Carry-Out
Clear & Preset Logic Control
LAB-wide signals control the logic for the register’s clear and preset
signals. The LE directly supports an asynchronous clear and preset
function. The register preset is achieved through the asynchronous load
of a logic high. The direct asynchronous preset does not require a NOT-
gate push-back technique. Stratix devices support simultaneous preset/
Altera Corporation
July 2005
2–13
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
