DC & Switching Characteristics
Table 4–36. Stratix Performance (Part 2 of 2) Notes (1), (2)
Resources Used
Performance
TriMatrix
LEs Memory
Blocks
-5
-6
-7
-8
Applications
DSP
Blocks
Speed Speed Speed Speed Units
Grade Grade Grade Grade
0
1
0
269.83 237.69 206.82 175.74
MHz
TriMatrix
memory
M-RAM
block
True dual-port
RAM 16K × 36 bit
Single port
RAM 32K × 18 bit
0
0
1
1
0
0
275.86 244.55 212.76 180.83
275.86 244.55 212.76 180.83
MHz
MHz
Simple dual-port
RAM 32K × 18 bit
0
1
0
275.86 244.55 212.76 180.83
MHz
True dual-port
RAM 32K × 18 bit
Single port
RAM 64K × 9 bit
0
0
1
1
0
0
287.85 253.29 220.36 187.26
287.85 253.29 220.36 187.26
MHz
MHz
Simple dual-port
RAM 64K × 9 bit
0
1
0
287.85 253.29 220.36 187.26
MHz
True dual-port
RAM 64K × 9 bit
DSP block 9 × 9-bit multiplier (3)
0
0
0
0
1
1
335.0 293.94 255.68 217.24
278.78 237.41 206.52 175.50
MHz
MHz
18 × 18-bit multiplier
(4)
36 × 36-bit multiplier
(4)
0
0
0
0
1
1
148.25 134.71 117.16 99.59
278.78 237.41 206.52 175.5
MHz
MHz
36 × 36-bit multiplier
(5)
18-bit, 4-tap FIR filter
0
0
0
1
4
278.78 237.41 206.52 175.50
141.26 133.49 114.88 100.28
MHz
MHz
Larger
Designs
8-bit, 16-tap parallel
FIR filter
58
8-bit, 1,024-point FFT 870
function
5
1
261.09 235.51 205.21 175.22
MHz
Notes to Table 4–36:
(1) These design performance numbers were obtained using the Quartus II software.
(2) Numbers not listed will be included in a future version of the data sheet.
(3) This application uses registered inputs and outputs.
(4) This application uses registered multiplier input and output stages within the DSP block.
(5) This application uses registered multiplier input, pipeline, and output stages within the DSP
block.
Altera Corporation
July 2005
4–21
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
