DC & Switching Characteristics
Table 4–39. DSP Block Internal Timing Microparameter Descriptions
Symbol
Parameter
tSU
tH
Input, pipeline, and output register setup time before clock
Input, pipeline, and output register hold time after clock
Input, pipeline, and output register clock-to-output delay
tCO
tINREG2PIPE9
Input Register to DSP Block pipeline register in 9 × 9-bit
mode
tINREG2PIPE18
Input Register to DSP Block pipeline register in 18 × 18-bit
mode
tPIPE2OUTREG2ADD
tPIPE2OUTREG4ADD
DSP Block Pipeline Register to output register delay in Two-
Multipliers Adder mode
DSP Block Pipeline Register to output register delay in Four-
Multipliers Adder mode
tPD9
Combinatorial input to output delay for 9 × 9
Combinatorial input to output delay for 18 × 18
Combinatorial input to output delay for 36 × 36
Minimum clear pulse width
tPD18
tPD36
tCLR
tCLKHL
Register minimum clock high or low time. This is a limit on
the min time for the clock on the registers in these blocks.
The actual performance is dependent upon the internal
point-to-point delays in the blocks and may give slower
performance as shown in Table 4–36 on page 4–20 and as
reported by the timing analyzer in the Quartus II software.
Altera Corporation
July 2005
4–23
Stratix Device Handbook, Volume 1
ALTERA [ ALTERA CORPORATION ]
