Timing Model
Skew on Input Pins
shows the package skews that were considered to get the
worst case I/O skew value. You can use these values, for example, when
calculating the timing budget on the input (read) side of a memory
interface.
Table 4–99. Package Skew on Input Pins
Package Parameter
Pins in the same I/O bank
Pins in top/bottom (vertical I/O) banks
Pins in left/right side (horizontal I/O) banks
Pins across the entire device
Worst-Case Skew (ps)
50
50
50
100
PLL Counter & Clock Network Skews
shows the clock skews between different clock outputs from
the Stratix device PLL.
Table 4–100. PLL Counter & Clock Network Skews
Parameter
Clock skew between two external clock outputs driven
by the same counter
Clock skew between two external clock outputs driven
by the different counters with the same settings
Dual-purpose PLL dedicated clock output used as I/O
pin vs. regular I/O pin
Clock skew between any two outputs of the PLL that
drive global clock networks
Note to
(1)
The Quartus II software models 270 ps of delay on the PLL dedicated clock
output (PLL6_OUT[3..0]p/n and
PLL5_OUT[3..0]p/n)
pins both when
used as clocks and when used as I/O pins.
Worst-Case Skew (ps)
100
150
270
150
I/O Timing Measurement Methodology
Different I/O standards require different baseline loading techniques for
reporting timing delays. Altera characterizes timing delays with the
required termination and loading for each I/O standard. The timing
information is specified from the input clock pin up to the output pin of
4–60
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
