Stratix Device Handbook, Volume 1
Global & Hierarchical Clocking 2–73
Global & Regional Clock Connections
from Side Pins & Fast PLL Outputs 2–85
from Top Clock Pins & Enhanced PLL
Outputs 2–86
Global Clock External I/O Timing
Parameters 4–35
Global Clock Network 2–74
Global Clocking 2–75
Packages 4–81
Wire-Bond
Packages 4–84
Phase & Delay Shifting 2–96
Phase Delay 2–96
PLL Clock Networks 2–73
Read/Write Clock Mode
2–49
in Simple Dual-Port Mode 2–50
Regional Clock 2–75
Independent Clock Mode 2–44
Input/Output
External I/O Timing Parameters 4–34
Regional Clock Bus 2–79
Regional Clock Network 2–75
Spread-Spectrum Clocking 2–98
Configuration 3–5
Clock Mode
2–46
Simple Dual-Port Mode 2–48
True Dual-Port Mode 2–47
Maximum Input & Output Clock Rates 4–76
Maximum Input Clock Rate
for CLK
32-Bit IDCODE 3–3
and Testing 3–1
Data Sources for Configuration 3–7
Local Update Mode 3–12
Local Update Transition Diagram 3–12
Operating Modes 3–5
Partial Reconfiguration 3–7
Remote Update 3–8
(0, 2, 9, 11) Pins in
Flip-Chip
Packages 4–77
Wire-Bond
Packages 4–79
(1, 3, 8, 10) Pins in
Remote Update Transition Diagram 3–11
Schemes 3–7
Flip-Chip
Packages 4–78
Wire-Bond
SignalTap II Embedded Logic Analyzer 3–5
Stratix FPGAs with JRunner 3–7
Control Signals 2–104
Packages 4–80
(7..4) & CLK(15..12) Pins in
Flip-Chip
D
DC Switching
Packages 4–76
Wire-Bond
Packages 4–78
Maximum Output Clock Rate
for PLL
Absolute Maximum Ratings 4–1
Bus Hold Parameters 4–16
Capacitance 4–17
DC & Switching Characteristics 4–1
External Timing Parameters 4–33
Operating Conditions 4–1
Performance 4–20
(1, 2, 3, 4) Pins in
Flip-Chip
Packages 4–83
Wire-Bond
Power Consumption 4–17
Recommended Operating Conditions 4–1
DDR
Double-Data Rate I/O Pins 2–111
Device Features
Packages 4–85
(5, 6, 11, 12) Pins in
Flip-Chip
EP1S10, EP1S20, EP1S25, EP1S30, 1–3
EP1S40, EP1S60, EP1S80, 1–3
Index–2
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
