DLL Jitter
Table 4–133. Fast PLL Specifications for -8 Speed Grades (Part 2 of 2)
Symbol
t
ARESET
Parameter
Minimum pulse width on
areset
signal
Min
10
Max
Unit
ns
Notes to
Tables 4–131
through
4–133:
(1)
(2)
(3)
(4)
See
“Maximum Input & Output Clock Rates” on page 4–76.
PLLs 7, 8, 9, and 10 in the EP1S80 device support up to 717-MHz input and output.
Use this equation (f
O U T
= f
I N
*
ml(n
× post-scale counter)) in conjunction with the specified f
I N P F D
and f
V C O
ranges to determine the allowed PLL settings.
When using the SERDES, high-speed differential I/O mode supports a maximum output frequency of 210 MHz
to the global or regional clocks (that is, the maximum data rate 840 Mbps divided by the smallest SERDES J factor
of 4).
Refer to the section
This parameter is for high-speed differential I/O mode only.
These counters have a maximum of 32 if programmed for 50/50 duty cycle. Otherwise, they have a maximum
of 16.
High-speed differential I/O mode supports
W
= 1 to 16 and
J
= 4, 7, 8, or 10.
(5)
(6)
(7)
(8)
DLL Jitter
Table 4–134
circuit.
Table 4–134. DLL Jitter for DQS Phase Shift Reference Circuit
Frequency (MHz)
197 to 200
160 to 196
100 to 159
±
100
±
300
±
500
DLL Jitter (ps)
f
For more information on DLL jitter, see the
DDR SRAM
section in the
Stratix Architecture
chapter of the
Stratix Device Handbook, Volume 1.
4–102
Stratix Device Handbook, Volume 1
Altera Corporation
July 2005
ALTERA [ ALTERA CORPORATION ]
