APEX 20KC Programmable Logic Device Data Sheet
Table 4. APEX 20KC FineLine BGA Package Options & I/O Count
Notes (1), (2)
Device
EP20K200C
EP20K400C
EP20K600C
EP20K1000C
Notes to
Tables 3
and
4:
(1)
(2)
(3)
I/O counts include dedicated input and clock pins.
APEX 20KC device package types include plastic quad flat pack (PQFP), 1.27-mm
pitch ball-grid array (BGA), and 1.00-mm pitch FineLine BGA
TM
packages.
This device uses a thermally enhanced package, which is taller than the regular
package. Consult the
Altera Device Package Information Data Sheet
for detailed
package size information.
484 Pin
376
672 Pin
1,020 Pin
488
(3)
508
(3)
508
(3)
588
708
Table 5. APEX 20KC QFP & BGA Package Sizes
Feature
Pitch (mm)
Area (mm
2
)
Length
×
Width (mm
×
mm)
208-Pin PQFP
0.50
924
30.4
×
30.4
240-Pin PQFP
0.50
1,218
34.9
×
34.9
356-Pin BGA
1.27
1,225
35.0
×
35.0
652-Pin BGA
1.27
2,025
45.0
×
45.0
Table 6. APEX 20KC FineLine BGA Package Sizes
Feature
Pitch (mm)
Area (mm )
Length
×
Width (mm
×
mm)
2
484 Pin
1.00
529
23
×
23
672 Pin
1.00
729
27
×
27
1,020 Pin
1.00
1,089
33
×
33
General
Description
Similar to APEX 20K and APEX 20KE devices, APEX 20KC devices offer
the MultiCore architecture, which combines the strengths of LUT-based
and product-term-based devices with an enhanced memory structure.
LUT-based logic provides optimized performance and efficiency for data-
path, register-intensive, mathematical, or digital signal processing (DSP)
designs. Product-term-based logic is optimized for complex
combinatorial paths, such as complex state machines. LUT- and product-
term-based logic combined with memory functions and a wide variety of
MegaCore and AMPP functions make the APEX 20KC architecture
uniquely suited for SOPC designs. Applications historically requiring a
combination of LUT-, product-term-, and memory-based devices can now
be integrated into one APEX 20KC device.
4
Altera Corporation
ALTERA [ ALTERA CORPORATION ]
