EP220 & EP224 Classic EPLDs
Figure 1. EP220 & EP224 Block Diagram
Numbers in parentheses refer to the pin-out number.
EP220
Global Clock
INPUT/CLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
I/O (19)
I/O (18)
I/O (17)
I/O (16)
I/O (15)
I/O (14)
I/O (13)
I/O (12)
Global
Bus
INPUT (11)
EP224
Global Clock
INPUT/CLK
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
INPUT
(1)
(2)
(3)
(4)
(5)
(6)
(7)
(8)
(9)
Macrocell 1
Macrocell 2
Macrocell 3
Macrocell 4
Macrocell 5
Macrocell 6
Macrocell 7
Macrocell 8
I/O (22)
I/O (21)
I/O (20)
I/O (19)
I/O (18)
I/O (17)
I/O (16)
I/O (15)
Global
Bus
INPUT (10)
INPUT (11)
INPUT (13)
INPUT (14)
INPUT (23)
The EP220 and EP224 architecture is based on a sum-of-products,
programmable-AND/fixed-OR structure. Each macrocell can be
individually programmed for combinatorial or registered output. An
inversion option allows each output to be configured for active-high or
active-low operation. Each I/O pin can be programmed to function as an
input, output, or bidirectional pin.
The EP220 and EP224 device architecture offers the following features:
s
s
Macrocells
High-frequency, low-skew global Clock
3
Altera Corporation
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