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EP220LC-7A 参数 Datasheet PDF下载

EP220LC-7A图片预览
型号: EP220LC-7A
PDF下载: 下载PDF文件 查看货源
内容描述: 经典EPLD中 [Classic EPLDs]
分类和应用: 可编程逻辑输入元件时钟
文件页数/大小: 16 页 / 400 K
品牌: ALTERA [ ALTERA CORPORATION ]
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EP220 & EP224 Classic EPLDs
Macrocells
Each macrocell includes a product-term block with 8
AND
product terms
feeding an
OR
gate. One product term is dedicated to the Output Enable
(OE) control of the tri-state buffer. The global logic array allows each
product term to connect to the true or complement of each input—36
inputs for the EP220, 44 inputs for the EP224—and I/O feedback signal.
See
Figure 2.
Figure 2. EP220 & EP224 Macrocell
Output Enable
D
Q
CLK
Inversion
Control
Programmable
Register
Feedback to
Logic Array
Pin, I/O, and
Macrocell Feedback
Feedback
Select
Macrocells can be individually configured for registered or combinatorial
operation, providing a mixed-mode operation not available in fixed-
architecture PAL devices. When registered output is selected, feedback
from the register to the logic array bypasses the output buffer. When
combinatorial output is selected, feedback comes from the I/O pin
through the output buffer, and can be used for bidirectional I/O. Unlike
PAL and GAL devices, all eight outputs on the EP220 and EP224 allow a
combinatorial feedback signal from the I/O pin to feed the logic array.
Data is clocked into the macrocell’s D register on the rising edge of the
global Clock.
4
Altera Corporation