FLEX 6000 Programmable Logic Device Family Data Sheet
General
Description
The Altera
®
FLEX 6000 programmable logic device (PLD) family provides
a low-cost alternative to high-volume gate array designs. FLEX 6000
devices are based on the OptiFLEX architecture, which minimizes die size
while maintaining high performance and routability. The devices have
reconfigurable SRAM elements, which give designers the flexibility to
quickly change their designs during prototyping and design testing.
Designers can also change functionality during operation via in-circuit
reconfiguration.
FLEX 6000 devices are reprogrammable, and they are 100% tested prior to
shipment. As a result, designers are not required to generate test vectors
for fault coverage purposes, allowing them to focus on simulation and
design verification. In addition, the designer does not need to manage
inventories of different gate array designs. FLEX 6000 devices are
configured on the board for the specific functionality required.
shows FLEX 6000 performance for some common designs. All
performance values shown were obtained using Synopsys DesignWare or
LPM functions. Special design techniques are not required to implement
the applications; the designer simply infers or instantiates a function in a
Verilog HDL, VHDL, Altera Hardware Description Language (AHDL), or
schematic design file.
Table 3. FLEX 6000 Device Performance for Common Designs
Application
LEs Used
-1 Speed
Grade
16-bit loadable counter
16-bit accumulator
24-bit accumulator
16-to-1 multiplexer (pin-to-pin)
16
×
16 multiplier with a 4-stage pipeline
Note:
(1)
This performance value is measured as a pin-to-pin delay.
Performance
-2 Speed
Grade
153
153
123
13.4
67
Units
-3 Speed
Grade
133
133
108
16.6
58
MHz
MHz
MHz
ns
MHz
16
16
24
10
592
172
172
136
12.1
84
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3
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