PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Block Diagram
Figure 1. PPC405EZ Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Power
Mgmt
32KB
SRAM
Timers
MMU
PowerPC
405 Core
JTAG
D-OCM
I-OCM
DCRs
OCM
Ctrl
UART
x2
Arbiter
On-chip Peripheral Bus (OPB)
CAN
x2
IIC/
BSC
SPI
GPIO Timer/ DAC
(SCP)
PWM
ADC
DCR
Bus
Trace
16KB D-Cache 16KB I-Cache
DMA
Controller
(4-Channel)
OPB/PLB
Bridges
MAL
Ethernet
10/100
USB 1.1
Host/Dev
IEEE
1588
PTP
Arbiter
Processor Local Bus (PLB) 64 bit, PLB3
PHY
External
Bus
Controller
NAND
Flash
Controller
MII
The PPC405EZ is designed using the IBM Microelectronics Blue Logic
TM
methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect
TM
Bus Architecture.
AMCC Proprietary
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
