PPC405EZ – PowerPC 405EZ Embedded Processor
Revision 1.27 - August 22, 2007
Preliminary Data Sheet
Address Maps
The PPC405EZ incorporates two address maps. The first address map defines the possible use of addressable
memory regions that the processor can access. The second address map defines Device Configuration Register
(DCR) addresses (numbers). The DCRs are accessed by software running on the PPC405EZ processor through
the use of
mtdcr
and
mfdcr
instructions.
Table 1. System Memory Address Map (4GB System Memory)
Function
General Use
Reserved
UART 0 Registers
UART 1 Registers
IIC Registers
OPB Arbiter Registers
GPIO 0 Controller Registers
GPIO 1 Controller Registers
EMAC Registers
Reserved
CAN 0 Registers
CAN 1 Registers
Chameleon Timer Registers
IEEE 1588 Sync Controller Registers
USB 1.1 Host Registers
Reserved
DAC Registers
ADC Registers
Serial Communication Port Registers
Reserved
USB 1.1 Device Registers
Reserved
Boot Address Range
Notes:
1. If peripheral bus boot is selected, peripheral bank 0 is automatically configured at reset to the address range listed above.
2. After the boot process, software may reassign the boot memory regions for other uses.
Subfunction
Start Address
0x 0000 0000
0x E000 0000
0x EF60 0300
0x EF60 0400
0x EF60 0500
0x EF60 0600
0x EF60 0700
0x EF60 0800
0x EF60 0900
0x EF60 0A00
0x EF60 1000
0x EF60 1800
0x EF60 2000
0x EF60 2800
0x EF60 3000
0x EF60 3200
0x EF60 3300
0x EF60 3400
0x EF60 3500
0x EF60 3600
0x EF64 0000
0x EF68 0000
0x FFE0 0000
End Address
0x DFFF FFFF
0x EF60 02FF
0x EF60 03FF
0x EF60 04FF
0x EF60 05FF
0x EF60 06FF
0x EF60 07FF
0x EF60 08FF
0x EF60 09FF
0x EF60 0FFF
0x EF60 17FF
0x EF60 1FFF
0x EF60 27FF
0x EF60 2FFF
0x EF60 31FF
0x EF60 32FF
0x EF60 33FF
0x EF60 34FF
0x EF60 35FF
0x EF63 FFFF
0x EF67 FFFF
0x FFDF FFFF
0x FFFF FFFF
2 MB
262KB
256B
256B
256B
2KB
2KB
2KB
2KB
512B
256B
256B
256B
256B
256B
256B
256B
Size
3.7GB
6
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
