405GPr – Power PC 405GPr Embedded Processor
Revision 2.04 – September 7, 2007
Data Sheet
PPC405GPr Embedded Controller Functional Block Diagram
Universal
Interrupt
Controller
Clock
Control
Reset
Timers
MMU
Power
Mgmt
DOCM
IOCM
OCM
SRAM
DCRs
OCM
Control
GPIO
IIC
UART
UART
PPC405
Processor Core
JTAG
16KB
D-Cache
DCU
Trace
ICU
DCR Bus
16KB
I-Cache
Arb
On-chip Peripheral Bus (OPB)
DMA
Controller
(4-Channel)
OPB
Bridge
MAL
Ethernet
Arb
Code
Decompression
(CodePack™)
Processor Local Bus (PLB)
SDRAM
Controller
External
Bus
Controller
External
Bus Master
Controller
PCI Bridge
13-bit addr
32-bit data
32-bit addr
32-bit data
66 MHz max (async)
33 MHz max (sync)
MII
The PPC405GPr is designed using the IBM
®
Microelectronics Blue Logic
TM
methodology in which major functional
blocks are integrated together to create an application-specific ASIC product. This approach provides a consistent
way to create complex ASICs using IBM CoreConnect
TM
Bus Architecture.
6
AMCC
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
