PPC440EP-3PBFFFCX 参数 Datasheet PDF下载

440EP – PPC440EP Embedded Processor

Revision 1.26 – April 25, 2007

Data Sheet

Signal Lists

The following table lists all the external signals in alphabetical order and shows the ball (pin) number on which the

signal appears. Multiplexed signals are shown with the default signal (following reset)

not

in brackets and alternate

signals in brackets. Multiplexed signals appear alphabetically multiple times in the list—once for each signal name

on the ball. The page number listed gives the page in “Signal Functional Description” on page 50 where the signals

in the indicated interface group begin. In cases where signals in the same interface group (for example, Ethernet)

have different names to distinguish variations in the mode of operation, the names are separated by a comma with

the primary mode name appearing first. These signals are listed only once, and appear alphabetically by the

primary mode name.

Table 3. Signals Listed Alphabetically (Sheet 1 of 24)

Signal Name

AGND

AV

DD

BA0

BA1

BankSel0

BankSel1

BankSel2

BankSel3

[BusReq][USB2TermSel]GPIO31

CAS

ClkEn

DM0

DM1

DM2

DM3

DM8

[DMAAck0][IRQ8]GPIO47

[DMAAck1][IRQ4]GPIO44

[DMAAck2][PerAddr06]GPIO01

[DMAAck3][PerAddr03]GPIO04

[DMAReq0][IRQ7]GPIO46

DMAReq1[IRQ5][ModeCtrl]

[DMAReq2][PerAddr07]GPIO00

[DMAReq3][PerAddr04]GPIO03

DQS0

DQS1

DQS2

DQS3

DQS8

[DrvrInh1]USB2LS0[RejectPkt]

[DrvrInh2]Halt

AMCC Proprietary

Ball

AE17

Power

AD17

AF03

DDR SDRAM

AF04

R04

R02

DDR SDRAM

R01

N01

AA23

J02

AF05

AE05

AD07

J01

L03

AF07

D18

G25

External Slave Peripheral

B06

C07

B24

AC12

External Slave Peripheral

C08

D08

AD09

AC08

K03

M04

AC06

Y25

System

C25

17

DDR SDRAM

DDR SDRAM

External Master Peripheral

DDR SDRAM

DDR SDRAM

Interface Group

Page