Revision 1.07 – October 4, 2007
440GP – Power PC 440GP Embedded Processor
Data Sheet
Signal Functional Description (Sheet 4 of 7)
Notes:
1. Receiver input has hysteresis
2. Must pull up (recommended value is 3kΩ to 3.3V, 10kΩ to 5V)
3. Must pull down (recommended value is 1kΩ)
4. If not used, must pull up (recommended value is 3kΩ to 3.3V)
5. If not used, must pull down (recommended value is 1kΩ)
6. Strapping input during reset; pull-up or pull-down required
Signal Name
Description
I/O
Type
Notes
External Master Peripheral Interface
Bus Request. Used when the PPC440GP needs to regain control
of peripheral interface from an external master.
5V tolerant
BusReq
ExtAck
O
O
I
3.3V LVTTL
External Acknowledgement. Used by the PPC440GP to indicate
that a data transfer occurred.
5V tolerant
3.3V LVTTL
External Request. Used by an external master to indicate it is
prepared to transfer data.
5V tolerant
3.3V LVTTL
ExtReq
ExtReset
HoldAck
HoldReq
PerClk
1, 4
Peripheral Reset. Used by an external master and by
synchronous peripheral slaves.
5V tolerant
3.3V LVTTL
O
O
I
Hold Acknowledge. Used by the PPC440GP to transfer ownership
of peripheral bus to an external master.
5V tolerant
3.3V LVTTL
Hold Request. Used by an external master to request ownership
of the peripheral bus.
5V tolerant
3.3V LVTTL
1, 5
1, 5
1, 4
Peripheral Clock. Used by an external master and by synchronous
peripheral slaves.
5V tolerant
3.3V LVTTL
O
I/O
External Error. Used as an input to record external master errors
and external slave peripheral errors.
5V tolerant
3.3V LVTTL
PerErr
UART Peripheral Interface
Serial clock input that provides an alternative to the internally
generated serial clock. Used in cases where the allowable
internally generated clock rates are not satisfactory. This input can
be individually connected to either or both UART0 and UART1.
5V tolerant
3.3V LVTTL
UARTSerClk
I
5V tolerant
UART0_Rx
UART0 Receive data.
I
O
I
1, 4
4
3.3V LVTTL
5V tolerant
3.3V LVTTL
UART0_Tx
UART0 Transmit data.
UART0 Data Carrier Detect.
UART0 Data Set Ready.
UART0 Clear To Send.
UART0 Data Terminal Ready.
UART0 Request To Send.
UART0 Ring Indicator.
UART1 Receive data.
5V tolerant
3.3V LVTTL
UART0_DCD
UART0_DSR
UART0_CTS
UART0_DTR
UART0_RTS
UART0_RI
6
5V tolerant
3.3V LVTTL
I
6
5V tolerant
3.3V LVTTL
I
1, 4
4
5V tolerant
3.3V LVTTL
O
O
I
5V tolerant
3.3V LVTTL
4
5V tolerant
3.3V LVTTL
1, 4
1, 4
1, 4
1, 4
5V tolerant
3.3V LVTTL
UART1_Rx
I/O
I/O
I/O
5V tolerant
3.3V LVTTL
UART1_Tx
UART1 Transmit data.
UART1 Data Set Ready or Clear To Send. The choice is
determined by a DCR register bit setting.
5V tolerant
3.3V LVTTL
UART1_DSR/CTS
AMCC
51
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
