440GR – PPC440GR Embedded Processor
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
Block Diagram
Figure 2. PPC440GR Functional Block Diagram
10
External
Interrupts
Clock
Control
Reset
Timers
MMU
UIC
PPC440
Power
Mgmt
DCRs
Processor Core
JTAG
32KB
D-Cache
Performance
Monitor
PLB4 (128 bits)
Trace
32KB
I-Cache
DCR Bus
GPIO
SPI
IIC
x2
BSC
UART
x4
On-chip Peripheral Bus (OPB)
DMA
Controller
PLB
Bridge
DMA
Controller
OPB
Bridge
GPT
PLB3 (64 bits)
Ethernet
10/100
x2
ZMII
MAL
DDR SDRAM
Controller
266MHz max
- 13-bit addr
- 32-bit data
PCI
Bridge
66MHz max
- 32 bits
- 6 devices
External
Peripheral
Controller
NAND
Flash
Controller
1 MII
or
2 RMII
or
2 SMII
66MHz max
- 30-bit addr
- 16-bit data
The PPC440GR is a system on a chip (SOC) using IBM CoreConnect Bus
™
Architecture.
AMCC Proprietary
5
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
