440GR – PPC440GR Embedded Processor
Revision 1.16 – July 19, 2006
Preliminary Data Sheet
PowerPC 440 Processor Core
The PowerPC 440 processor core is designed for high-end applications: RAID controllers, SAN, iSCSI, routers,
switches, printers, set-top boxes, etc. It implements the Book E PowerPC embedded architecture and uses the
128-bit version of IBM’s on-chip CoreConnect Bus Architecture.
Features include:
• Up to 667MHz operation
• PowerPC Book E architecture
• 32KB I-cache, 32KB D-cache
– UTLB Word Wide parity on data and tag address parity with exception force
• Three logical regions in D-cache: locked, transient, normal
• D-cache full line flush capability
• 41-bit virtual address, 36-bit (64GB) physical address
• Superscalar, out-of-order execution
• 7-stage pipeline
• 3 execution pipelines
• Dynamic branch prediction
• Memory management unit
– 64-entry, full associative, unified TLB with optional parity
– Separate instruction and data micro-TLBs
– Storage attributes for write-through, cache-inhibited, guarded, and big or little endian
• Debug facilities
– Multiple instruction and data range breakpoints
– Data value compare
– Single step, branch, and trap events
– Non-invasive real-time trace interface
• 24 DSP instructions
– Single cycle multiply and multiply-accumulate
– 32 x 32 integer multiply
– 16 x 16 -> 32-bit MAC
AMCC Proprietary
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AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
