Revision 1.23 - Sept 21, 2006
Preliminary Data Sheet
DDR SDRAM Read Operation
The Read of the incoming Data from the SDRAM is done on the rising and falling edges of the differential DQS
signal. The Data must be centered to these edges for correct operation.
The PPC440SPe can delay with very fine granularity the DQS through the programming of the
MCIF0_RODC[RQFD] register field.
DDR SDRAM MemClkOut0 and Read Clock Delay
In order to accommodate timing variations introduced by the system designs using this chip, the three-stage data
path shown below is used to eliminate metastability and allow data sampling to be adjusted for minimum latency.
The data are stored in the 8 Flip Flops of the Stage 1, such that it can be transferred later within a 8X period.
Figure 9. DDR SDRAM Read Data Path
Ext FeedBack
Signals
DDR 1X Clock
FF: Flip-Flop
MemDCFdbkD
Driver
Coarse Delay
FeedBack
Signal Gen
CAS Lat Delay
Read Start
Read Latency adjust circuit
MCIF0_RFDC[RFFD]
Rec
Fine Delay
DDR 1X Clock
Stage 2 Store
Oversampling
Fine Delay
MemDCFdbkR
Feedback
Data Capture
Window
0
DQS aligned
FBK signal
Cycles
Delay
+1
MCIF0_RFDC[RFOS]
T1 T2 T3 T4
MCIF0_RDCC[RDSS]
adjust
Oversampling
Clock
1
7
Q2_Ovs
0
2
4
6
Package
pins
Mux
FF
D
FF
FF
C
Q2
Compare
(x64)
Mux
Read FIFO
Upper
PLB bus
[0:63]
DQ
Data
(x64)
DQS Rising
Edge Sync
Stage 1
FF
1
3
5
7
Stage 2
FF
FF
(x64)
C
Lower
Stage 3
Q3
D
FF
PLB bus
[64:127]
DQS
(Diff)
Programmed
Read DQS
Delay
DQS Falling
Edge Sync
DDR 1X Clock
PLB 1X Clock
MCIF0_RQDC[RQFD]
74
AMCC Proprietary
AMCC [ APPLIED MICRO CIRCUITS CORPORATION ]
