PPC440SPE-AGB533C 参数 Datasheet PDF下载

Revision 1.23 - Sept 21, 2006

Preliminary Data Sheet

The following example shows the timing relationship between SDRAM DDR Data at the input pin and the store of

the Data in stage 1.

Figure 11. DDR SDRAM Read Cycle Timing—Example

Oversampling Guard Band

DDR 1X Clock

DDR 2X Clock

Memclk (Diff.)

DQS at

MemCntl Pin

Data at Pin

D0

D1

D2

D3

D4

D5

D6

D7

D8

D9

Feedback

Output

1X DDR Clk cycle

Delayed DQS

T1

T2

Store 1st Data in Stage 2

T3

T4

Data Out Stage 1 (0)

Data Out Stage 1 (1)

Data out Stage 1 (2)

Valid

High

Data Out Stage 2

Low

D1

D0

D2

D3

PLB 1X Clock

76

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