rising edge of CE or WE (whichever happens first)
begins programming. Upon executing the Embedded
Program Algorithm command sequence the system is
not
required to provide further controls or timings. The
device will automatically provide adequate internally
generated program pulses and verify the programmed
cell margin.
The automatic programming operation is completed
when the data on DQ7 is equivalent to data written to
this bit (see Write Operation Status section) at which
time the device returns to the read mode and ad-
dresses are no longer latched. Therefore, the device
requires that a valid address to the device be supplied
by the system at this particular instance of time. Hence,
Data Polling must be performed at the memory location
which is being programmed.
Any commands written to the chip during this period
will be ignored.
Programming is allowed in any sequence and across
sector boundaries. Beware that a data “0” cannot be
programmed back to a “1”. Attempting to do so may
cause the device to exceed programming time limits
(DQ5 = 1) or result in an apparent success, according
to the data polling algorithm, but a read from reset/read
mode will show that the data is still “0”. Only erase
operations can convert “0”s to “1”s.
Figure 1 illustrates the Embedded Programming Algorithm
using typical command strings and bus operations.
Sector Erase
Sector erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the sector erase command. The sector
address (any address location within the desired sector)
is latched on the falling edge of WE, while the command
(data) is latched on the rising edge of WE. A time-out
of 80
µs
from the rising edge of the last sector erase
command will initiate the sector erase command(s).
Multiple sectors may be erased concurrently by writing
the six bus cycle operations as described above. This
sequence is followed with writes of the Sector Erase
command to addresses in other sectors desired to be
concurrently erased. The time between writes must be
less than 80
µs,
otherwise that command will not be ac-
cepted. It is recommended that processor interrupts be
disabled during this time to guarantee this condition.
The interrupts can be re-enabled after the last Sector
Erase command is written. A time-out of 80
µs
from the
rising edge of the last WE will initiate the execution of
the Sector Erase command(s). If another falling edge of
the WE occurs within the 80
µs
time-out window the
timer is reset. (Monitor DQ3 to determine if the sector
erase window is still open, see section DQ3, Sector
Erase Timer.) Any command other than Sector Erase
or Erase Suspend during this period resets the device
to read mode, ignoring the previous command string. In
that case, restart the erase on those sectors and allow
them to complete. (Refer to the Write Operation Status
section for Sector Erase Timer operation.) Loading the
sector erase buffer may be done in any sequence and
with any number of sectors (1 to 8).
Sector erase does
not
require the user to program the
device prior to erase. The device automatically
programs all memory locations in the sector(s) to be
erased prior to electrical erase. When erasing a sector
or sectors the remaining unselected sectors are not
affected. The system is
not
required to provide any
controls or timings during these operations.
The automatic sector erase begins after the 80
µs
time
out from the rising edge of the WE pulse for the last
sector erase command pulse and terminates when the
data on DQ7 is “1" (see Write Operation Status section)
at which time the device returns to read mode.
During
the execution of the Sector Erase command, only the
Erase Suspend and Erase Resume commands are
allowed. All other commands will be ignored.
Data poll-
ing must be performed at an address within any of the
sectors being erased.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
Chip Erase
Chip erase is a six bus cycle operation. There are two
“unlock” write cycles. These are followed by writing the
“setup” command. Two more “unlock” write cycles are
then followed by the chip erase command.
Chip erase does
not
require the user to program the
device prior to erase. Upon executing the Embedded
Erase Algorithm command sequence the device auto-
matically will program and verify the entire memory for
an all zero data pattern prior to electrical erase. The
chip erase is performed sequentially one sector at a
time. The system is not required to provide any controls
or timings during these operations.
The automatic erase begins on the rising edge of the
last WE pulse in the command sequence and termi-
nates when the data on DQ7 is “1” (see Write Operation
Status section) at which time the device returns to read
the mode.
Figure 2 illustrates the Embedded Erase Algorithm
using typical command strings and bus operations.
10
Am29F040
AMD [ ADVANCED MICRO DEVICES ]
