DATA SHEET
DEVICE BUS OPERATIONS
This section describes the requirements and use of the
device bus operations, which are initiated through the
internal command register. The command register it-
self does not occupy any addressable memory loca-
tion. The register is composed of latches that store the
commands, along with the address and data informa-
tion needed to execute the command. The contents of
the register serve as inputs to the internal state ma-
chine. The state machine outputs dictate the function of
the device. The appropriate device bus operations
table lists the inputs and control levels required, and the
resulting output. The following subsections describe
each of these operations in further detail.
Table 1. Am29F800B Device Bus Operations
DQ8–DQ15
Operation
Read
Write
CMOS Standby
TTL Standby
Output Disable
Hardware Reset
Temporary Sector Unprotect
(See Note)
CE#
L
L
V
CC
± 0.5 V
H
L
X
X
OE#
L
H
X
X
H
X
X
WE#
H
L
X
X
H
X
X
RESET#
H
H
V
CC
± 0.5 V
H
H
L
V
ID
A0–A18
A
IN
A
IN
X
X
X
X
A
IN
DQ0–DQ7
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
D
IN
BYTE#
= V
IH
D
OUT
D
IN
High-Z
High-Z
High-Z
High-Z
D
IN
BYTE#
= V
IL
High-Z
High-Z
High-Z
High-Z
High-Z
High-Z
X
Legend:
L = Logic Low = V
IL
, H = Logic High = V
IH
, V
ID
= 12.0
±
0.5 V, X = Don’t Care, D
IN
= Data In, D
OUT
= Data Out, A
IN
= Address In
Note:
See the sections on Sector Group Protection and Temporary Sector Unprotect for more information.
Word/Byte Configuration
The BYTE# pin controls whether the device data I/O
pins DQ15–DQ0 operate in the byte or word configura-
tion. If the BYTE# pin is set at logic ‘1’, the device is in
word configuration, DQ15–DQ0 are active and con-
trolled by CE# and OE#.
If the BYTE# pin is set at logic ‘0’, the device is in byte
configuration, and only data I/O pins DQ0–DQ7 are ac-
tive and controlled by CE# and OE#. The data I/O pins
DQ8–DQ14 are tri-stated, and the DQ15 pin is used as
an input for the LSB (A-1) address function.
command is necessary in this mode to obtain array
data. Standard microprocessor read cycles that as-
sert valid addresses on the device address inputs
produce valid data on the device data outputs. The
device remains enabled for read access until the
command register contents are altered.
See “Reading Array Data” for more information. Refer
to the AC Read Operations table for timing specifica-
tions and to the Read Operations Timings diagram for
the timing waveforms. I
CC1
in the DC Characteristics
table represents the active current specification for
reading array data.
Requirements for Reading Array Data
To read array data from the outputs, the system must
drive the CE# and OE# pins to V
IL
. CE# is the power
control and selects the device. OE# is the output control
and gates array data to the output pins. WE# should re-
main at V
IH
.
The internal state machine is set for reading array
data upon device power-up, or after a hardware reset.
This ensures that no spurious alteration of the mem-
ory content occurs during the power transition. No
Writing Commands/Command Sequences
To write a command or command sequence (which in-
cludes programming data to the device and erasing
sectors of memory), the system must drive WE# and
CE# to V
IL
, and OE# to V
IH
.
An erase operation can erase one sector, multiple sec-
tors, or the entire device. The Sector Address Tables in-
dicate the address space that each sector occupies. A
“sector address” consists of the address bits required
to uniquely select a sector. See the “Command Defini-
November 2, 2006 21504E5
Am29F800B
9
AMD [ ADVANCED MICRO DEVICES ]
