DATA SHEET
internal register (which is separate from the memory
array) on DQ7–DQ0. Standard read cycle timings apply
in this mode. Refer to the Autoselect Mode and Autose-
information.
I
CC2
in the DC Characteristics table represents the
active current specification for the write mode. The “AC
tables and timing diagrams for write operations.
access timings provide new data when addresses are
changed. While in sleep mode, output data is latched
and always available to the system. I
CC4
in the DC
mode current specification.
RESET#: Hardware Reset Pin
The RESET# pin provides a hardware method of reset-
ting the device to reading array data. When the
RESET# pin is driven low for at least a period of t
RP
, the
device
immediately terminates
any operation in
progress, tristates all output pins, and ignores all
read/write commands for the duration of the RESET#
pulse. The device also resets the internal state
machine to reading array data. The operation that was
interrupted should be reinitiated once the device is
ready to accept another command sequence, to
ensure data integrity.
Current is reduced for the duration of the RESET#
pulse. When RESET# is held at V
SS
±0.3 V, the device
draws CMOS standby current (I
CC4
). If RESET# is held
at V
IL
but not within V
SS
±0.3 V, the standby current will
be greater.
The RESET# pin may be tied to the system reset cir-
cuitry. A system reset would thus also reset the Flash
memory, enabling the system to read the boot-up firm-
ware from the Flash memory.
If RESET# is asserted during a program or erase oper-
ation, the RY/BY# pin remains a “0” (busy) until the
internal reset operation is complete, which requires a
time of t
READY
(during Embedded Algorithms). The
system can thus monitor RY/BY# to determine whether
the reset operation is complete. If RESET# is asserted
when a program or erase operation is not executing
(RY/BY# pin is “1”), the reset operation is completed
within a time of t
READY
(not during Embedded Algo-
rithms). The system can read data t
RH
after the
RESET# pin returns to V
IH
.
Refer to the AC Characteristics tables for RESET#
parameters and to Figure 14 for the timing diagram.
Program and Erase Operation Status
During an erase or program operation, the system may
check the status of the operation by reading the status
bits on DQ7–DQ0. Standard read cycle timings and I
CC
read specifications apply. Refer to “Write Operation
Standby Mode
When the system is not reading or writing to the device,
it can place the device in the standby mode. In this
mode, current consumption is greatly reduced, and the
outputs are placed in the high impedance state, inde-
pendent of the OE# input.
The device enters the CMOS standby mode when the
CE# and RESET# pins are both held at V
CC
±
0.3 V.
(Note that this is a more restricted voltage range than
V
IH
.) If CE# and RESET# are held at V
IH
, but not within
V
CC
±
0.3 V, the device will be in the standby mode, but
the standby current will be greater. The device requires
standard access time (t
CE
) for read access when the
device is in either of these standby modes, before it is
ready to read data.
If the device is deselected during erasure or program-
ming, the device draws active current until the
operation is completed.
I
CC3
in the DC Characteristics table represents the
standby current specification.
Automatic Sleep Mode
The automatic sleep mode minimizes Flash device
energy consumption. The device automatically enables
this mode when addresses remain stable for t
ACC
+ 30
ns. The automatic sleep mode is independent of the
CE#, WE#, and OE# control signals. Standard address
Output Disable Mode
When the OE# input is at V
IH
, output from the device is
disabled. The output pins are placed in the high imped-
ance state.
10
Am29LV004B
21522D5 October 11, 2006
AMD [ ADVANCED MICRO DEVICES ]
