AMD
BLOCK DIAGRAM (continued)
Am7969
(X1)
Serial In+ (SERIN+)
Serial In– (SERIN–)
Media
Interface
Oscillator
and
Clock Gen.
(X2)
PLL Clock
Generator
Shifter
Decoder Latch
(DMS) Data Mode Select
Data Decoder
Byte Sync
Logic
(CNB) Catch Next Byte
(IGM) I-Got-Mine
Output Latch
N
(VLTN)
Violation
M
(CLK) Clock
(DSTRB) Data Strobe
(CSTRB) Command Strobe
07370F-2
Data Command
Note:
N can be 8, 9, or 10 bits Total of N + M = 12
CONNECTION DIAGRAMS
Top View
Am7968
DIPs
SEROUT-
ACK
STRB
SEROUT+
SEROUT–
V
CC2
(ECL)
V
CC1
(TTL)
V
CC3
(CML)
RESET
DMS
TLS
TSERIN
CI0
CI1
DI9/CI2
DI5
DI4
DI3
DI2
DI1
DI0
GND1 (TTL)
GND2 (CML)
X1
X2
CLK
DI6
DI7
DI8/CI3
07370F-3
LCC/PLCC
SEROUT+
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
STRB
ACK
DI5
DI4
4
V
CC2
(ECL)
V
CC1
(TTL)
V
CC3
(TTL)
RESET
DMS
TLS
TSERIN
5
6
7
8
9
10
11
3
2
1 28 27 26
25
24
23
22
21
20
19
DI2
DI1
DI0
GND1 (TTL)
GND2 (CML)
X1
X2
07370F-4
12 13 14 15 16 17 18
DI9/CI2
DI8/CI3
CI0
CI1
DI7
DI6
CLK
Note:
Pin 1 is marked for orientation.
2
Am7968/Am7969
DI3
AMD [ ADVANCED MICRO DEVICES ]
