Jitter Tolerance Definition and Test
The Receive Timing—Start of Reception Clock Acqui-
sition waveform diagram shows the internal timing rela-
tionships implemented for decoding Manchester data
in the Am7992B. The Am7992B utilizes a clock capture
circuit to align its internal data strobe with an incoming
bit stream. The clock acquisition circuitry requires four
valid bits with the values 1010. Clock is phase locked to
the negative transition at BCC of the second “0” in
thepattern.
Since data is strobed at 1/4 bit time, Manchester tran-
sitions that shift from their nominal placement through
1/4 bit time will result in improperly decoded data. For
IEEE 802.3/Ethernet, this results in the loss of a mes-
sage. With this as the criterion for an error, a definition
of “jitter handling” is:
That peak deviation from nominal input transition
approaching or crossing 1/4 bit cell position for
which the Am7992B will properly decode data.
Four events of signal are needed to adequately test the
ability of the Am7992B to decode data properly from
the Manchester bit stream. For each of the four events,
two time points within a received message are tested
(See Input Jitter Timing Waveforms):
1. Jitter tolerance at clock acquisition, the measure of
clock capture (case 1–4).
2. Jitter tolerance within a message after the analogue
PLL has reduced clock acquisition error to a mini-
mum (case 5–8).
The four events to test are shown in the Input Jitter
Timing Waveform diagram. They are:
1. BCC jitter for a 01-bit pattern
2. BCC jitter for a 10-bit pattern
3. BCB jitter for an 11-bit pattern
4. BCB jitter for an X0-bit pattern
The test signals utilized to jitter the input data are arti-
ficial in that they may not be realizable on networks (ex-
amples are cases 2, 3, and 4 at clock acquisition).
However, each pattern relates to setup and hold time
measurements for the data decode register (Figure 5).
Receive+ and Receive– are driven with the inputs
shown to produce the zero crossing distortion at the dif-
ferential inputs for the applicable test. Cases 4 and 8
require only a single zero to implement when tested at
the end of message.
Levels used to test jitter are within the common-mode
and differential-mode ranges of the receive inputs and
also are available from automatic test equipment. It is
assumed that the incoming message is asynchronous
with the local TCLK frequency for the Am7992B. This
ensures that proper clock acquisition has been estab-
lished with random phase and frequency error in in-
coming messages. An additional condition placed on
the jitter tolerance test is that it must meet all test re-
quirements within 10 ms after power is applied. This
forces the Am7992B crystal oscillator to start and lock
the analog PLL to within acceptable limits for receiving
from a cold start.
Case 1 of the test corresponds to the expected
Manchester data at clock acquisition, and average val-
ues for clock leading jitter tolerance are 21.5 ns. For
cases 5 through 8, average values are 24.4 ns. Cases
5 through 8 are jittered at bit times 55 or 56 as applica-
ble. The Am7992B, then, has on average 0.6 ns static
phase error for the noise-free case.
10
Am7992B
AMD [ ADVANCED MICRO DEVICES ]
