15-0
NRDAL
Contains the lower 16 bits of the
next receive descriptor address
pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR30: Base Address of Transmit Ring Lower
Bit
31-16
15-0
Name
RES
BADXL
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
base address of the Transmit
Ring.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR31: Base Address of Transmit Ring Upper
Bit
31-16
15-0
Name
RES
BADXU
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
base address of the Transmit
Ring.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR32: Next Transmit Descriptor Address Lower
Bit
31-16
15-0
Name
RES
NXDAL
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
next transmit descriptor address
pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR33: Next Transmit Descriptor Address Upper
Bit
31-16
15-0
Name
RES
NXDAU
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next transmit descriptor address
pointer.
CSR27: Next Receive Descriptor Address Upper
Bit
31-16
15-0
Name
RES
NRDAU
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
next receive descriptor address
pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR28: Current Receive Descriptor Address Lower
Bit
31-16
15-0
Name
RES
CRDAL
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the lower 16 bits of the
current receive descriptor ad-
dress pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR29: Current Receive Descriptor Address Upper
Bit
31-16
15-0
Name
RES
CRDAU
Description
Reserved locations. Written as
zeros and read as undefined.
Contains the upper 16 bits of the
current receive descriptor ad-
dress pointer.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
130
Am79C978
AMD [ ADVANCED MICRO DEVICES ]
