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AM79C978KC/W 参数 Datasheet PDF下载

AM79C978KC/W图片预览
型号: AM79C978KC/W
PDF下载: 下载PDF文件 查看货源
内容描述: 单芯片1/10 Mbps的PCI家庭网络控制器 [Single-Chip 1/10 Mbps PCI Home Networking Controller]
分类和应用: 控制器PC
文件页数/大小: 261 页 / 3499 K
品牌: AMD [ ADVANCED MICRO DEVICES ]
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15-12
11-0
RES
CRBC
Reserved locations. Read and
written as zeros.
Current Receive Byte Count.
This field is a copy of the BCNT
field of RMD1 of the current re-
ceive descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR43: Current Transmit Status
Bit
Name
Description
Reserved locations. Written as
zeros and read as undefined.
Current Transmit Status. This
field is a copy of bits 31-16 of
TMD1 of the current transmit de-
scriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR44: Next Receive Byte Count
Bit
Name
Description
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
Next Receive Byte Count. This
field is a copy of the BCNT field of
RMD1 of the next receive de-
scriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR45: Next Receive Status
Bit
Name
Description
Reserved locations. Written as
zeros and read as undefined.
Next Receive Status. This field is
a copy of bits 31-16 of RMD1 of
the next receive descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR46: Transmit Poll Time Counter
Bit
Name
Description
Reserved locations. Written as
zeros and read as undefined.
31-16 RES
15-0
CXST
CSR41: Current Receive Status
Bit
31-16
15-0
Name
RES
CRST
Description
Reserved locations. Written as
zeros and read as undefined.
Current Receive Status. This
field is a copy of bits 31-16 of
RMD1 of the current receive de-
scriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
CSR42: Current Transmit Byte Count
Bit
31-16
15-12
11-0
Name
RES
RES
CXBC
Description
Reserved locations. Written as
zeros and read as undefined.
Reserved locations. Read and
written as zeros.
Current Transmit Byte Count.
This field is a copy of the BCNT
field of TMD1 of the current trans-
mit descriptor.
These bits are read/write acces-
sible only when either the STOP
or the SPND bit is set. These bits
are unaffected by H_RESET,
S_RESET, or STOP.
31-16 RES
15-12 RES
11-0
NRBC
31-16 RES
15-0
NRST
31-16 RES
132
Am79C978