ISA Bus Interface For External ISA Peripherals
The ISA interface consists of a subset of ISA-compati-
ble bus signals, allowing for the connection of 8- or
16-bit devices supporting ISA-compatible I/O, memory,
and DMA cycles. The following features are supported:
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8.2944-MHz maximum bus clock speed
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Programmable DMA clock speed up to 16 MHz
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8-bit and 16-bit ISA I/O and memory cycles (ISA
memory is non-cacheable)
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Direct connection to 3- or 5-volt peripherals
Eight programmable IRQ input signals are available.
These interrupts can be routed via software to any
available PC/AT-compatible interrupt channel.
Two programmable DMA channels are available for ex-
ternal DMA peripherals. These DMA channels can be
routed to software to any available ISA DMA channel.
VESA Local (VL) Bus Interface Supports 32-Bit
Memory and I/O Targets
The VESA local (VL) bus controller provides the sig-
nals and associated timing necessary to support a sin-
gle VESA compliant VL-bus target. Multiple VL-bus
targets can be supported using external circuitry to
allow multiple VL devices to share the VL_LDEV sig-
nal. This allows the ÉlanSC400 and ÉlanSC410 micro-
controllers to operate as a normal VL-bus motherboard
controller, in accordance with the
VL-Bus Standard 2.0
.
On the ÉlanSC400 microcontroller, the VL-bus is
available only when the internal graphics controller is
disabled.
The microcontroller’s VL-bus controller includes the
following features:
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33-MHz operation at 3.3 V
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32-bit data bus
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Burst-mode transfers
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Register control of local bus reset
VESA bus mastering and DMA transfers to and from
the VL-bus target are not supported. VL memory is
non-cacheable.
SYSTEM CONSIDERATIONS
might be used in a minimal system design.
signs for each microcontroller and the features that are
traded for others because of pin multiplexing.
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The ÉlanSC400 and ÉlanSC410 microcontrollers
support a maximum of 4 banks of 32-bit DRAM, but
because the RAS and CAS signals for the high
word and for banks 2 and 3 are traded for keyboard
row signals, the minimum system would have one
or two banks of DRAM (either Bank 0 or Bank 1)
populated with 16-bit DRAMs. The MA12 signal for
asymmetrical support is also traded with a keyboard
row signal.
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Because the VL-bus and the graphics controller
share control signals on the ÉlanSC400 microcon-
troller, use of the internal graphics controller is
traded with having an external VL-bus on that mi-
crocontroller.
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If either 32-bit DRAMs, 32-bit ROMs, or the VL-bus
is enabled, the internal graphics controller on the
ÉlanSC400 microcontroller is unavailable because
of internal design constraints.
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The ÉlanSC400 and ÉlanSC410 microcontrollers
provide an absolute minimum of dedicated ISA con-
trol signals. Any additional ISA controls are traded
with GPIOs or keyboard rows and columns.
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The SD buffer shares control signals with some of
the GPIOs. This buffer controls the high word of the
D data bus (D31–D16). Note that using the SD
buffer is optional. The high word of the D data bus
can be hooked up directly to devices that want the
SD data bus (SD15–SD0). Buffering aids in voltage
translation or isolation for heavy loading.
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The R32BFOE signal buffers the high word of the D
data bus (D31–D16) for 32-bit ROMs. The control
signal associated with the ROM32 buffer is shared
with a keyboard row.
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On the ÉlanSC400 microcontroller, the parallel port
is traded for PC Card Socket B. It requires an exter-
nal buffer and latch.
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The serial and infrared ports share the same inter-
nal UART. Real-time switching between the two is
supported; however, only one port is available at
any given time.
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ROMCS2 is not connected to a dedicated pin. Soft-
ware can enable and map it to any of the 15
GPIO_CS signals.
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Élan™SC400 and ÉlanSC410 Microcontrollers Data Sheet
AMD [ ADVANCED MICRO DEVICES ]
