AMIS-720639:
600dpi CIS Sensor Chip
6.0 Switching Characteristics at 25
°
C
Data Sheet
Since these image sensors are applied in a multiple-length line array with a wide range in scanning speeds, two types of output video
amplifiers are used. Three video output circuits are discussed in Section 7.0. There are only two basic types of video output circuits.
One is a current sensing amplifier and the other is a charge storing buffer amplifier. Simplified block diagrams show their interface
connections with the image sensors. They were also used to measure the specifications given in this data sheet. The timing
relationships among these two different video signals and the image sensor’s two input clocks, its SP, its shift register clock (CP) and its
shift register output (EOS), are shown in two diagrams, Figure 3 and its supplement, Figure 4. The two timing diagrams are
accompanied with two tables of timing symbol’s specification. These symbols graphically define the timing relationships among the
waveforms in the timing diagrams; see Figure 3. The switching specifications are given in Table 6. Except for the analog video output,
the rest are digital clock waveforms. Their levels are +5V CMOS compatible. The video signal, Iout, timing is specified in Table 6. Its
amplitude was specified in Table 2.
Figure 3: Timing Diagram of the AMIS-720639 Sensor
Table 6: Timing Symbol's Definition
Item
Clock cycle time
Clock pulse width
Clock duty cycle
Data setup time
Data hold time
Prohibit crossing time
SP turn on and off
EOS rise delay
EOS fall delay
Signal delay time to peak
Signal fall time delay
Notes:
(1)
(2)
(3)
(4)
(5)
(6)
Symbol
(1)
to
(2)
tw
(3)
Dty
tds
tdh
(4)
Tprh
(5)
Tonoff
terdl
tefdl
(6)
tdtp
(6)
tftd
Min.
154
77
25
20
20
Mean
Max.
10000
75
50
20
80
75
20
80
Units
ns
ns
%
ns
ns
ns
Note 5
ns
ns
ns
ns
Minimum is specified at the maximum clock frequency of 6.5MHz.
Since the clock pulse width varies with frequency, tw will vary according to duty cycle. This minimum is specified at 6.5MHz and 50 percent duty cycle.
The clock duty cycle typically is 25 percent. At 5.0MHz or higher 50 percent is recommended. This recommendation is to keep the die-to-die FPN to a minimum
between die transitions in CIS operation.
Tprh is the time where the SP high is prohibited. No consecutive falling clock edges are allowed during one cycle of SP. Otherwise, two SPs or more will load into
the shift register for each negative going clock edge. Multiple SPs loaded into the shift register will access proportional numbers of multiple pixels simultaneously at
each clock cycle.
The recommended time to start and stop the SP is between two consecutive rising clock edges, indicated by the tonoff arrows.
These values, tdtp and tftd, are measurements from the circuit in Figure 6, which is essentially the pulse voltage across the 50Ω resistor. This is one of the circuits
employed to convert the video signal current to voltage. See the discussion on the two amplifier configurations in Section 7.0.
AMI Semiconductor
– May 06, M-20569-001
www.amis.com
5
AMI [ AMI SEMICONDUCTOR ]
