XPressArray-II
0.15
m
m Structured ASIC
Figure 12 shows the LVDS PLL configuration which supports
high-speed serial I/O applications. The reference divider
supports a range of 1 to 2049 while the feedback divider is
Data Sheet
limited to a range of 1 to 33. The PLL contains integral test
hardware to facilitate silicon testing and in-circuit PLL tuning.
The PLL requires a dedicated power and ground pad pair.
RFFCLK
+N
Phase
Compare
FOUT90
FOUT180
FOUT270
FOUT360
+M
LVDS PLL
LOCK
Figure 12: LVDS PLL
9.0 RTL Hand-Off Flow
XPressArray-II synthesis libraries are available for leading
commercial synthesizers, including Synplicity
®
Synplify ASIC
and Synopsys
®
Design Compiler.
With the RTL hand-off flow, you can submit your RTL
description, scripts and timing constraints to AMIS. AMIS will
check, synthesize, layout, and achieve timing closure on your
design. Typically if Synplify Pro was used for the FPGA design,
then Synplify ASIC will be used for the ASIC design. Likewise
if FPGA DC was used, then Design Compiler is used for the
ASIC re-synthesis.
10.0 NETRANS
®
Conversion Flow
XPressArray-II devices are fully supported by AMI
Semiconductor's proven NETRANS flow. AMIS has over 19
years experience using NETRANS to convert over 1700 FPGA
and third party ASIC designs to AMIS ASICs.
Inputs to the NETRANS flow include the netlist, test benches
and timing constraints. Over 70 different device types and
netlist formats are supported.
Mapping libraries are fully verified by a process which includes
formal verification of each primitive function.
AMI Semiconductor
- Preliminary
www.amis.com
10
AMI [ AMI SEMICONDUCTOR ]
