XPressArray-II
0.15
m
m Structured ASIC
8.0 Phased-Locked Loop (PLL) Description
PLLs are embedded into the XPressArray-II bases to perform
advanced clock frequency synthesis operations, minimize
clock insertion delay and generate phase taps. Each PLL can
be configured as a general purpose or LVDS PLL.
Figure 7 shows the general purpose PLL configuration. All
dividers have a range of 1 to 2049. In normal mode, as shown
Data Sheet
in Figure 8, the PLL performs classical "M over N" frequency
synthesis application. When the output frequency is an integer
multiple or division of the input frequency precise phase control
allows fine adjustment of the phase relationship of the output
to the input. In this example, locations B and C are phase
controlled with respect to A. The phase relationship of A and D
is inferred.
REFCLK
+N
Phase
Compare
Phase
Shift
+A
FOUTA
+B
FOUTB
+M
FBFCLK
General Purpose PLL
LOCK
Figure 7: General Purpose PLL
PAD
+N
A
Phase
Compare
Phase
Shift
+B
C
DFF
+A
B
D
PAD
+M
General Purpose PLL
Figure 8: General Purpose PLL in Normal Mode
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