A29L800A Series
Autoselect Mode
The autoselect mode provides manufacturer and device
identification, through identifier codes output on I/O
7
- I/O
0
.
This mode is primarily intended for programming equipment to
automatically match a device to be programmed with its
corresponding programming algorithm. However, the
autoselect codes can also be accessed in-system through the
command register.
When using programming equipment, the autoselect mode
requires V
ID
(11.5V to 12.5 V) on address pin A9. Address pins
A6, A1, and A0 must be as shown in Autoselect Codes (High
Voltage Method) table. In addition, when verifying sector
protection, the sector address must appear on the appropriate
highest order address bits. Refer to the corresponding Sector
Address Tables. The Command Definitions table shows the
remaining address bits that are don't care. When all necessary
bits have been set as required, the programming equipment
may then read the corresponding identifier code on I/O
7
-
I/O
0
.To access the autoselect codes in-system, the host
system can issue the autoselect command via the command
register, as shown in the Command Definitions table. This
method does not require V
ID
. See "Command Definitions" for
details on using the autoselect mode.
Table 4. A29L800A Autoselect Codes (High Voltage Method)
Description
Mode
CE
OE
WE
A18
to
A12
X
A11
to
A10
X
A9
A8
to
A7
X
A6
A5
to
A2
X
A1
A0
I/O
8
to
I/O
15
X
B3h
I/O
7
to
I/O
0
37h
1Ah
1Ah
9Bh
9Bh
7Fh
Manufacturer ID: AMIC
Device ID:
A29L800A
(Top Boot Block)
Device ID:
A29L800A
(Bottom Boot Block)
Continuation ID
Word
Byte
Word
L
L
H
V
ID
L
L
L
L
L
H
X
X
V
ID
X
L
X
L
H
X
B3h
L
Byte
L
L
H
X
X
V
ID
X
L
X
L
H
X
L
H
X
X
V
ID
X
L
X
H
H
X
L=Logic Low= V
IL
, H=Logic High=V
IH
, SA=Sector Address, X=Don’t Care.
Note: The autoselect codes may also be accessed in-system via command sequences.
Hardware Data Protection
The requirement of command unlocking sequence for
programming or erasing provides data protection against
inadvertent writes (refer to the Command Definitions table). In
addition, the following hardware data protection measures
prevent accidental erasure or programming, which might
otherwise be caused by spurious system level signals during
V
CC
power-up transitions, or from system noise. The device is
powered up to read array data to avoid accidentally writing
data to the array.
Logical Inhibit
Write cycles are inhibited by holding any one of
OE
=V
IL
,
CE
= V
IH
or
WE
= V
IH
. To initiate a write cycle,
CE
and
WE
must be a logical zero while
OE
is a logical one.
Power-Up Write Inhibit
If
WE
=
CE
= V
IL
and
OE
= V
IH
during power up, the device
does not accept commands on the rising edge of
WE
. The
internal state machine is automatically reset to reading array
data on the initial power-up.
Write Pulse "Glitch" Protection
Noise pulses of less than 5ns (typical) on
OE
,
CE
or
WE
do
not initiate a write cycle.
(June, 2005, Version 1.1)
9
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
