A43L2616B
Simplified Truth Table
Command
CKEn-1 CKEn
CS
RAS
CAS
WE
DQM BA0 A10 A9~A0, Notes
BA1 /AP
A11
Register
Refresh
Mode Register Set
Auto Refresh
Self
Refresh
Entry
Exit
H
H
L
H
H
H
H
X
H
L
H
X
X
X
X
X
L
H
L
H
L
L
L
H
L
L
L
L
L
L
H
X
L
H
L
H
L
H
L
L
H
X
L
H
H
H
L
H
X
X
H
X
V
X
X
H
X
L
L
H
X
H
L
L
H
H
H
X
X
H
X
V
X
H
X
L
H
H
X
H
H
L
L
L
H
X
X
H
X
V
X
H
X
X
X
X
X
X
X
X
V
V
V
V
OP CODE
X
X
Row Addr.
L
H
L
H
X
L
H
X
X
Column
Addr.
Column
Addr.
1,2
3
3
3
3
4
4
4,5
4
4,5
Bank Active & Row Addr.
Read &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
Write &
Auto Precharge Disable
Column Addr. Auto Precharge Enable
Burst Stop
Precharge
Bank Selection
Both Banks
Clock Suspend or
Active Power Down
Entry
Exit
Entry
Precharge Power Down Mode
Exit
DQM
No Operation Command
H
H
L
H
L
H
H
X
X
X
X
X
X
X
V
X
X
X
6
X
(V = Valid, X = Don’t Care, H = Logic High, L = Logic Low)
Note :
1. OP Code: Operand Code
A0~A11, BA0, BA1: Program keys. (@MRS)
2. MRS can be issued only at both banks precharge state.
A new command can be issued after 2 clock cycle of MRS.
3. Auto refresh functions as same as CBR refresh of DRAM.
The automatical precharge without Row precharge command is meant by “Auto”.
Auto/Self refresh can be issued only at both precharge state.
4. BA0, BA1 : Bank select address.
If both BA1 and BA0 are “Low” at read, write, row active and precharge, bank A is selected.
If both BA1 is “Low” and BA0 is “High” at read, write, row active and precharge, bank B is selected.
If both BA1 is “High” and BA0 is “Low” at read, write, row active and precharge, bank C is selected.
If both BA1 and BA0 are “High” at read, write, row active and precharge, bank D is selected.
If A10/AP is “High” at row precharge, BA1 and BA0 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read write command cannot be issued.
Another bank read write command can be issued at every burst length.
6. DQM sampled at positive going edge of a CLK masks the data-in at the very CLK (Write DQM latency is 0) but
masks the data-out Hi-Z state after 2 CLK cycles. (Read DQM latency is 2)
(December, 2009, Version 1.3)
8
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
