A617308 Series
Timing Waveforms (continued)
Write Cycle 2
(Chip Enable Controlled)
tWC
Address
3
tAW
tWR
5
tCW
CE1
CE2
(4)
(4)
1
tAS
2
tWP
WE
tDW
tDH
DIN
7
tWHZ
DOUT
Notes: 1. tAS is measured from the address valid to the beginning of Write.
2. A Write occurs during the overlap (tWP) of a low , a high CE2 and a low WE .
CE1
or WE going high or CE2 going low to the end of the Write cycle.
3. tWR is measured from the earliest of
CE1
4. If the
low transition or the CE2 high transition occurs simultaneously with the WE low transition or after
CE1
the WE transition, outputs remain in a high impedance state.
5. tCW is measured from the later of going low or CE2 going high to the end of Write.
CE1
6. OE is continuously low. ( OE = VIL)
7. Transition is measured ±200mV from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(January, 2000, Version 0.2)
8
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
