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A63L83361 参数 Datasheet PDF下载

A63L83361图片预览
型号: A63L83361
PDF下载: 下载PDF文件 查看货源
内容描述: 256K X 36位同步高速SRAM突发计数器和流过的数据输出 [256K X 36 Bit Synchronous High Speed SRAM with Burst Counter and Flow-through Data Output]
分类和应用: 计数器静态存储器
文件页数/大小: 16 页 / 263 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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A63L83361
Notes:
1.
2.
All voltages refer to GND.
Overshoot: V
IH
+2V for t
t
KC
/2.
Undershoot: V
IL
-0.7V for t
t
KC
/2.
Power-up: V
IH
+2 and VCC
1.7V
for t
200ms
I
CC1
is given with no output current. I
CC1
increases with greater output loading and faster cycle times.
Test conditions assume the output loading shown in Figure 1, unless otherwise specified.
For output loading, C
L
= 5pF, as shown in Figure 2. Transition is measured
±
150mV from steady state voltage.
At any given temperature and voltage condition, t
KQHZ
is less than t
KQLZ
and t
OEHZ
is less than t
QELZ
.
A WRITE cycle is defined by at least one Byte Write enable LOW and ADSP HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ( ADSC or ADV LOW) or ADSP LOW for the
required setup and hold times.
OE has no effect when a Byte Write enable is sampled LOW.
This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP or ADSC is LOW and the chip is enabled. All other synchronous inputs must meet the setup and
hold times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be
valid at each rising edge of CLK when either ADSP or ADSC is LOW to remain enabled.
The load used for V
OH
, V
OL
testing is shown in Figure 2. AC load current is higher than the given DC values.
AC I/O curves are available upon request.
"Device Deselected" means device is in POWER-DOWN mode, as defined in the truth table. "Device Selected" means
device is active (not in POWER-DOWN mode).
MODE pin has an internal pulled-up, and ZZ pin has an internal pulled-down. All of then exhibit an input leakage
current of 10
µ
A.
Snooze (ZZ) input is recommended that users plan for four clock cycles to go into SLEEP mode and four clocks to
emerge from SLEEP mode to ensure no data is lost.
3.
4.
5.
6.
7.
8.
9.
10.
11.
12.
13.
PRELIMINARY (July, 2005, Version 0.0)
10
AMIC Technology, Corp.