A63L83361
Timing Waveforms (continued)
t
KC
CLK
t
KH
t
ADSS
ADSP
t
ADSS
ADSC
t
AS
ADDRESS
A1
t
AH
A2
BYTE W RITE signals are ignored
for first cycle when ADSP initiates burst
BW E,BW 1-BW 4
(NOTE 5)
t
WS
GW
t
CES
CE
(NOTE 2)
t
ADVS
ADV
(NOTE 4)
ADV suspends burst
t
ADVH
t
CEH
t
WH
A3
t
WS
t
WH
t
ADSH
ADSC extends burst
t
ADSS
t
ADSH
t
ADSH
t
KL
OE
(NOTE 3)
t
DS
t
DH
D(A1)
t
OEHZ
D(A2)
D(A2+1)
(NOTE 1)
D(A2+1)
D(A2+2)
D(A2+3)
D(A3)
D(A3+1)
D(A3+2)
DIN
High-Z
DOUT
BURST READ
Single W RITE
Extended BURST W RITE
Don't Care
Undefined
Write Timing
Notes: 1. D(A2) refers to output from address A2. D(A2+1) refers to output from the internal burst address immediately
following A2.
2. Timing for CE2 and CE2 is identical to that for CE . As shown in the above diagram, when CE is LOW, CE2
is LOW and CE2 is HIGH. When CE is HIGH, CE2 is HIGH and CE2 is LOW.
3. OE must be HIGH before the input data setup, and held HIGH throughout the data hold period. This prevents
input/output data contention for the period prior to the time Byte Write enable inputs are sampled.
4. ADV must be HIGH to permit a Write to the loaded address.
5. Byte Write enables are decided by means of a Write truth table.
PRELIMINARY (July, 2005, Version 0.0)
12
AMIC Technology, Corp.
AMICC [ AMIC TECHNOLOGY ]
