LP62S16256E-I Series
AC Test Conditions
Input Pulse Levels
Input Rise And Fall Time
Input and Output Timing Reference Levels
Output Load
0.4V to 2.4V
5 ns
1.5V
See Figures 1 and 2
TTL
TTL
C
L
30pF
C
L
5pF
* Including scope and jig.
* Including scope and jig.
Figure 1. Output Load
Figure 2. Output Load for t
CLZ
,
t
OLZ
,
t
CHZ
,
t
OHZ
,
t
WHZ
,
and t
OW
Data Retention Characteristics
(T
A
= -40°C to 85°C)
Symbol
V
DR
Parameter
VCC for Data Retention
Min.
2.0
Typ.
-
Max.
3.6
Unit
V
Conditions
CE
≥
VCC - 0.2V
I
CCDR
Data Retention Current
-
0.08
3*
µA
VCC = 2.0V,
CE
≥
VCC - 0.2V
V
IN
≥
0V
t
CDR
t
R
t
VR
Chip Disable to Data Retention Time
Operation Recovery Time
VCC Rising Time from Data Retention
Voltage to Operating Voltage
I
CCDR
: max.
0
t
RC
5
-
-
-
-
-
-
ns
ns
ms
See Retention Waveform
* LP62S16256E-55LLI / 70LLI
1µA at T
A
= 0°C to + 40°C
(January, 2002, Version 2.0)
11
AMIC Technology, Inc.
AMICC [ AMIC TECHNOLOGY ]
