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LP62S16256EV-55LLI 参数 Datasheet PDF下载

LP62S16256EV-55LLI图片预览
型号: LP62S16256EV-55LLI
PDF下载: 下载PDF文件 查看货源
内容描述: 256K x 16位的低电压CMOS SRAM [256K X 16 BIT LOW VOLTAGE CMOS SRAM]
分类和应用: 静态存储器
文件页数/大小: 15 页 / 168 K
品牌: AMICC [ AMIC TECHNOLOGY ]
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LP62S16256E-I Series  
Package Information  
48LD CSP ( 6 x 8 mm ) Outline Dimensions  
(48TFBGA)  
unit: mm  
TOP VIEW  
BOTTOM VIEW  
Ball#A1 CORNER  
S
0.10  
C
S
0.25 C A B  
Ball*A1 CORNER  
b (48X)  
6
5 4 3 2 1  
1
2 3 4 5 6  
A
B
C
D
E
F
A
B
C
D
E
F
G
H
G
H
B
e
D
1
A
SIDE VIEW  
D
0.20(4X)  
C
SEATING PLANE  
Dimensions in mm  
Symbol  
MIN. NOM. MAX.  
A
A1  
A2  
D
1.04  
0.20  
0.48  
5.90  
7.90  
---  
1.14  
0.25  
0.53  
6.00  
8.00  
3.75  
5.25  
0.75  
0.35  
1.24  
0.30  
0.58  
6.10  
8.10  
---  
E
D1  
E1  
e
---  
---  
---  
---  
b
0.30  
0.40  
Note:  
1. THE BALL DIAMETER, BALL PITCH, STAND-OFF & PACKAGE THICKNESS  
ARE DIFFERENT FROM JEDEC SPEC MO192 (LOW PROFILE BGA FAMILY).  
2. PRIMARY DATUM C AND SEATING PLANE ARE DEFINED BY THE SPHERICAL  
CROWNS OF THE SOLDER BALLS.  
3. DIMENSION b IS MEASURED AT THE MAXIMUM.  
THERE SHALL BE A MINIMUM CLEARANCE OF 0.25mm BETWEEN THE EDGE OF  
THE SOLDER BALL AND THE BODY EDGE.  
4. BALL PAD OPENING OF SUBSTRATE IS F 0.3mm (SMD)  
SUGGEST TO DESIGN THE PCB LAND SIZE AS F 0.3mm (NSMD)  
(January, 2002, Version 2.0)  
14  
AMIC Technology, Inc.