LP62S16512-T Series
Timing Waveforms
Read Cycle 1
(1, 2, 4)
t
RC
Address
t
AA
t
OH
t
OH
D
OUT
Read Cycle 2
(1, 2, 3)
t
RC
Address
t
AA
CS
1
CS
2
t
ACS1 ,
t
ACS2
t
CLZ1 ,
t
CLZ2
t
BE
t
CHZ1 ,
t
CHZ2
HB, LB
t
BLZ
5
t
BHZ
5
OE
t
OHZ
5
t
OE
t
OLZ
5
D
OUT
Notes:
1. WE is high for Read Cycle.
2. Device is continuously enabled CS
1
= V
IL
, or CS
2
= V
IH
, HB = V
IL
and, or LB = V
IL
.
3. Address valid prior to or coincident with CS
1
and ( HB and, or LB ) transition low or CS
2
transition High.
4. OE = V
IL
.
5. Transition is measured
±500mV
from steady state. This parameter is sampled and not 100% tested.
PRELIMINARY
(March, 2002, Version 0.2)
7
AMIC Technology, Inc.